Vhdl And Fpga Development For Beginners And Intermediates

Tags: FPGA

Learn how to create a VHDL design that can be simulated and implemented on a Xilinx or Altera FPGA development board.

Last updated 2022-01-10 | 4

- Understand the design process for implementing a digital design onto a FPGA
- Learn how to simulate a design in Altera’s ModelSim and Xilinx Isim
- Learn how to use Xilinx ISE tool to program FPGA

What you'll learn

Understand the design process for implementing a digital design onto a FPGA

Learn how to simulate a design in Altera’s ModelSim and Xilinx Isim

Learn how to use Xilinx ISE tool to program FPGA

Debug a VHDL design using ModelSim

Simulate a VHDL design using ModelSim

Familiarize yourself with Altera and Xilinx tools

Program a FPGA

* Requirements

* Purchase a BASYS 3 or BASYS 2 FPGA Development Board
* Download Xilinx ISE webpack if your using the BASYS 2
* but we will cover that in this course!
* Download Vivado if your using the BASYS 3 board
* we will cover this in the course!
* Basic understanding of Binary Notation
* Basic understanding of Hexadecimal Notation
* Basic understanding of Logic Gates

Description

This course supports both the Xilinx and Altera FPGA development boards.

VHDL and FPGA Development for Beginners and Intermediates is a course that is designed to teach students how to create and successfully simulate their VHDL design. We will also be implementing these designs on a Xilinx BASYS 3 or BASYS 2 FPGA development board so that the students can see their designs actually running. This course starts from beginning to end in teaching the user how to turn their digital logic design into VHDL designs that can be simulated in ModelSim or ISim and then implemented on an FPGA development board. This course also covers how to use Altera's tools so students are not limited to Xilinx development boards.

Course Structure:

This course contains over 20 lectures that will teach students the syntax and structure of VHDL. The student will be able to understand the syntax and use of specific VHDL keywords by taking this course. There are lectures included in each lab to give a background on the digital logic circuit the student will be implementing.

This course contains 7 labs that are designed so that the student will learn how to develop VHDL code. For each lab I will give the student a set of VHDL files that they will have to modify or change in order to get the project to simulate correctly in ModelSim and so they can implement the design on their FPGA board. These labs are design to help the students learn VHDL by actually coding it themselves.

Please message me before you sign up for this course!

Who this course is for:

Engineering Students
Engineering Managers
Digital Logic Enthusists
Individuals pursuing Electrical Engineering
Anyone who wants to take it for fun!

Course content

19 sections • 97 lectures

Contact Information 2 lectures

Contact Information Preview 1 page

This contains the information required to contact me, please download and use this if you have any questions.

Extra Resources for Using FPGAs Preview 00:07

If you are interested in learning more about FPGA development, these links contain resources that cover more advanced FPGA development topics.

Introduction 2 lectures

Introduction to the Course Preview 03:42

This lecture introduces this course, I will introduce myself as well as explain what will be covered in this course. The course layout is explained in this course.

Introduction to VHDL Preview 05:53

Introduction to VHDL and the different ways you can use VHDL. This will give you a better understanding of what VHDL is doing and how it differentiates from a software programming language. This is the programming language we are using for this course.

VHDL Data Types 8 lectures

Data Types Introduction Preview 02:56

This lecture introduces the various data types used in the VHDL language. All of these data types are then explained more thoroughly in the later lectures.

Signals / Variables / Constants Preview 04:27

This lecture talks about what variables, signals, and constants are and how they are used in the VHDL language.

Unsigned / Signed Data Types Preview 05:15

This lecture discusses signed and unsigned data types in the VHDL language.

Standard Logic Vector / Standard Logic Preview 04:27

This lecture discusses the VHDL data types standard logic vector and standard logic.

Integer / Boolean Data Types Preview 03:46

This lecture talks about the Integer and Boolean data types in VHDL.

Initializing Values in VHDL Preview 07:32

This lecture walks through an example VHDL file that shows various data types in VHDL being initialized.

Data Type Examples in VHDL Designs Part 1 Preview 05:46

This lecture walks through a VHDL design while talking about the various data types being used in the VHDL language.

Data Type Examples in VHDL Designs Part 2 Preview 02:19

This lecture takes students through an example VHDL design and discusses the various data types being used throughout the design.

VHDL Syntax 8 lectures

VHDL Syntax Introduction Preview 00:46

This lecture introduces the VHDL Syntax section and explains everything that will be covered in this section.

If Statement / Case Statement Preview 07:34

If statements and case statements are commonly used in various programming languages. These statements are also used in VHDL and I will explain how in this lecture.

For Loop / While Loop Preview 06:33

This lecture walks through and discusses how for loops and while loops are used in VHDL.

VHDL For Loop Example Preview 03:50

This lecture explains the differences between a for loop in VHDL verses a for loop in a software programming language such as c++.

When Else Statement With Select When Statement Preview 04:16

This lecture discusses two different statements in VHDL, the when-else statement as well as the with-select-when statement.

VHDL Processes and Concurrent Statement Preview 05:04

In VHDL things happen concurrently by nature, however with the use of processes and variables we can make things happen sequentially. In this lecture I will discuss the difference between them.

VHDL Syntax Design Example Preview 03:20

This lecture walks through a VHDL design and discusses the layout and structure of the VHDL syntax.

1 VHDL Basics

This is a quiz that goes over the material covered in section 2 VHDL Language Basics

VHDL Coding Structure 7 lectures

Organizing Your VHDL Designs Preview 03:00

This lecture shows students a way they can organize their VHDL designs. As you create more designs it becomes important to organize them in a way it's easy to find and re-use your designs.

VHDL Design Structure Preview 05:15

This lecture talks about the various aspects of a VHDL design and the structure of these designs.

VHDL Design Architecture Styles Preview 09:01

This lecture discusses the different architecture design styles used in VHDL designs.

Data Flow Architecture Example - Full Adder Preview 03:25

This lecture walks through a full adder VHDL design. this full adder design is implemented using a data flow architecture style.

Behavioral Architecture Example - Full Adder Preview 02:06

This lecture walks through a full adder VHDL design. this full adder design is implemented using a behavioral architecture style.

Concept of VHDL Modeling Preview 00:27

VHDL Coding Structure

This quiz is used to test your understanding of VHDL coding structures.

Test Bench 4 lectures

Test Benches Introduction Preview 04:11

This lecture explains what a test bench is and how they are used in the VHDL language.

Test Bench Structure Walkthrough Preview 02:35

This lecture walks through the design of a test bench and explains the structure of a VHDL test bench.

Walkthrough of a Completed Test Bench Preview 03:09

This lecture walks through a completed test bench as an example of how a test bench is constructed.

VHDL Test Benches

This quiz covers material explain in the Test Bench Section of this course.

Implementing State Machines in VHDL 2 lectures

State Machine Introduction Preview 03:59

This lecture introduces state machine in VHDL and explains how they are used.

Designing a State Machine Preview 00:54

This article explains how to design a state machine. There are various ways to design a state machine and this article covers one of them.

FPGA Development Boards 8 lectures

Supported FPGA Development Boards Preview 01:50

This article lists various FPGA development boards that students could use to complete this course. FPGA development boards not listed in this article can still be used, just message me and see if your board will work!

BASYS 3 Board Overview Preview 04:42

This lecture is an overview of the BASYS 3 development board.

BASYS 3 Board User Guide Preview 19 pages

This is the user guide provided by digilent that explains all the different components and aspects of the BASYS 3 development board.

BASYS 3 Board Schematic Preview 7 pages

The schematic of the BASYS 3 development board.

BASYS 2 Board Preview 01:48

An overview of the BASYS 2 FPGA development board.

BASYS 2 Board User Guide Preview 12 pages

This lecture contains the BASYS 2 user manual provided by digilent.

BASYS 2 Board Schematic Preview 7 pages

This is the actual schematic of the BASYS 2 development board.

BASYS 2 Board Overview Preview 04:08

This lecture gives an overview of the BASYS 2 development board.

Altera Tools 4 lectures

Altera Tools Introduction Preview 02:11

This is a brief overview of a few of the Altera tools available.

ModelSim VHDL Simulation Tool Preview 05:32

Lecture 8 is a step by step tutorial on how to use ModelSim to simulate and verify the VHDL designs.

Quartus II FPGA Development Tool Preview 04:00

A step by step tutorial on how to create a project in Quartus II and implement the design on an Altera FPGA or CPLD.

Altera Tools

This quiz is used to test your knowledge of Altera's toolset.

Xilinx Tools 6 lectures

Xilinx Tools Introduction Preview 01:09

A brief overview of a few of the Xilinx tools available.

Download the Vivado Tool Suite for the BASYS 3 Preview 07:24

ISim VHDL Simulation Tool Preview 02:13

Here we introduces you to ISim and how to simulate your design using ISim

Xilinx ISE FPGA Development Tool Preview 07:44

A detailed step by step tutorial on how to use Xilinx's ISE tool to take your VHDL design and create a programming file to load onto a CPLD or FPGA.

Programming The BASYS 2 FPGA Development Board Preview 01:38

This will show you how to load the FPGA programming file onto the BASYS 2 board.

Xilinx Tools

This quiz will test your knowledge of the Xilinx tool set.

Lab 1 - Full Adder 4 lectures

Introduction Preview 02:08

A introduction to the full adder.

BASYS 3 Full Adder Demonstration Preview 14:46

BASYS 2 Full Adder Demonstration Preview 01:37

This video shows a full adder implemented on a BASYS 2 board.

BASYS 2 Full Adder Solution Preview 14:05

If you are struggling with getting the Lab 1 Demonstration to work, Lab 1 Solution is a walk through to help you complete this lab as a step-by-step guide.

Lab 2 - Shift Register 4 lectures

Introduction Preview 02:17

A introduction to shift registers and their uses.

BASYS 3 Shift Register Demonstration Preview 02:10

BASYS 2 Shift Register Demonstration Preview 03:18

Shift Register Completed Design Preview 00:34

The completed VHDL design of the Shift Register.

Lab 3 - Universal Shift Register 5 lectures

Introduction Preview 01:48

A introduction to the universal shift register and many other shift registers.

BASYS 3 Universal Shift Register Demonstration Preview 03:39

BASYS 2 Universal Shift Register Demonstration Preview 05:53

A demonstration showing a universal shift register implemented on the BASYS 2 board.

BASYS 2 Universal Shift Register Solution Preview 21:50

If you are struggling with getting the Lab 3 Demonstration to work, Lab 3 Solution is a walk through to help you complete this lab as a step-by-step guide.