Hls Combinational Circuits

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Logic Design with Vitis-HLS

Last updated 2022-01-10 | 4.6

- Designing combinational logic circuits with C/C++ language using the HLS approach
- Understanding the basic concepts of High-Level Synthesis (HLS)
- Using HLS concepts for designing combinational logic circuits

What you'll learn

Designing combinational logic circuits with C/C++ language using the HLS approach
Understanding the basic concepts of High-Level Synthesis (HLS)
Using HLS concepts for designing combinational logic circuits
HLS design flow for FPGAs
Working with Xilinx Vitis-HLS and Vivado suite Toolsets
How to generate RTL hardware IPs using Vitis-HLS
Writing C-testbench in HLS
Implementing two exciting projects with HLS

* Requirements

* Understanding the basic concepts of C/C++ coding
* Understanding the basic concepts of logic operators (e.g.
* AND
* OR
* XOR
* SHIFT )
* BASYS3 evaluation board
* Xilinx Vitis-HLS and Vivado (download Vivado ML Edition
* or Vivado Design Suite - HLx Editions for Windows or Linux)

Description

This course is an elementary introduction to high-level synthesis (HLS) design flow. The goals of the course are describing, debugging and implementing combinational logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog). The HLS is recently used by several industry leaders (such as Nvidia and Google) to design their hardware and software platforms. The HLS design flow is the future of hardware design, which quickly becomes a must-have skill for every hardware or software engineer who is keen on utilising FPGAs for their exceptional performance and low power consumption.

It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. This course is the first to build the HLS design flow and skills along with the digital logic circuit concepts from scratch. Throughout the course, you will follow several examples describing HLS concepts and techniques. The course contains numerous quizzes and exercises for you to practice and master the proposed methods and approaches.

This course is the first of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on combinational circuits. The other courses in the series will explain how to use HLS in designing sequential logic circuits, algorithm acceleration, and hybrid CPU+ FPGA heterogeneous systems.


Who this course is for:

  • Hardware engineers
  • Software engineers who are interested in FPGAs
  • Lecturers, researchers, professors who want to use FPGA-based HLS in lectures, courses or research
  • Digital Logic enthusiasts

Course content

14 sections • 110 lectures

Prologue 2 lectures

Introduction Preview 05:08

Course Structure Preview 05:11

FPGA Concepts 10 lectures

Introduction Preview 02:06

Features and Applications Preview 02:14

Design Approach Preview 04:20

FPGA Platform vs CPU Platform Preview 05:46

FPGA Basic Preview 03:54

LUT Preview 03:29

Flip-Flop And Other Elements Preview 04:40

Basys3 FPGA Development Board Preview 05:05

Why HLS? Preview 04:17

Hardware and Software Analogy Preview 05:05

Hardware/Software Setup 5 lectures

Introduction Preview 02:10

Vivado-HLx Preview 04:49

Vivado and Vivado-HLS Preview 03:55

Install Vivado-HLx Preview 03:41

Test Installation Preview 06:39

Basic Output 12 lectures

Introduction Preview 03:20

Output Configuration Preview 02:43

Controller Concept Preview 02:25

HLS Design Overview Preview 02:53

HLS Design Flow Preview 05:45

HLS C/C++ Design Preview 04:04

HLS Ports Preview 03:36

HLS LAB Preview 08:53

Vivado Preview 04:34

Vivado LAB Preview 07:24

Basis3 Board Preview 04:19

Exercises Preview 00:44

Basic Input/Output 7 lectures

Introduction Preview 02:36

Configuration Preview 01:44

Controller Concept Preview 01:59

HLS Ports Preview 04:32

HLS LAB Preview 04:17

Vivado LAB Preview 06:10

Exercise Preview 00:43

Combinational Circuit 13 lectures

Introduction Preview 02:53

Definition Preview 02:58

Logic Gates Preview 03:32

Propagation Delay Preview 04:53

Binary Adder Delay Preview 03:46

Combinational Circuit in HLS Preview 04:32

Combinational Circuit in Vivado-HLS Preview 04:54

Combinational Circuit in Vivado Preview 06:19

Functions Preview 06:10

Dataflow Preview 05:33

Traffic Light Preview 06:30

Traffic Light-Vivado-HLx Preview 10:14

Exercises Preview 00:41

C/C++ Testbench 6 lectures

Introduction Preview 02:09

Definition Preview 03:25

Simulation Flow Preview 03:29

HLS Testbench Coding Preview 04:00

Vivado HLS Preview 08:10

Exercises Preview 00:15

Data Type 11 lectures

Introduction Preview 03:16

Native Datatypes Preview 03:13

Synthesis Preview 06:54

Bit Precision: Declaration Preview 04:30

Bit Precision: Initializing Preview 03:59

Bit Precision: Assignment Preview 05:08

Bit Precision: Print Preview 02:36

Bit Precision: Bitlevel Preview 03:49

Bit Precision: Bitwise Logical Operators Preview 03:23

Bit Precision: Shift/Rotate Preview 02:21

Exercises Preview 00:29

Conditional Statements 9 lectures

Introduction Preview 02:16

Definition Preview 02:28

Multiplexer Preview 02:13

Multiplexer: General Case Preview 03:55

HLS Preview 03:49

Encoder/Decoder Preview 04:46

Leading One Preview 02:58

LAB Preview 15:42

Exercises Preview 00:26

Seven Segments 11 lectures

Introduction Preview 03:35

Definition Preview 02:32

7-Segment Codes Preview 01:31

Basys3 Preview 02:42

One Digit Preview 02:53

BCD Code Preview 02:25

BCD TO 7-segment: Div/Mod Preview 05:34

BCD TO 7-Segment: Double Dabble Preview 04:50

Two Digits Preview 03:39

LAB Preview 14:23

Exercises Preview 00:26

Combinational Loops 10 lectures

Introduction Preview 02:47

Definition Preview 05:20

Loop Unroll Preview 02:49

Loop Unroll Conditions Preview 03:22

Parity Bit: Definition Preview 03:52

Parity Bit: Design Preview 02:15

Parity Bit: Design Optimisation Preview 02:36

Parity Bit: HLS Preview 03:45

Parity Bit: Vivado-HLS Preview 05:15

Exercises Preview 00:16

Integer Arithmetic 8 lectures

Introduction Preview 02:49

Definition Preview 04:42

Overloading Preview 04:16

Timing Constraint Preview 06:15

DSP Resources Preview 04:22

Resource Constraint Preview 10:39

Division/Modulus Preview 08:21

Exercises Preview 00:39

Projects: Home_Alarm_System 3 lectures

Definition Preview 03:37

Code Structure Preview 05:01

Vivado-HLx Preview 11:17

Project: Simple Calculator 3 lectures

Definition Preview 02:16

Code Structure Preview 05:16

Vivado-HLx Preview 13:24