Fpgavhdl Course

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Tags: FPGA

A course designed to teach FPGA design and digital design (basic and intermediate) using VHDL as a language

Last updated 2022-01-10 | 4

- Basics of Digital Design
- Combinational Logic design using VHDL
- Sequential Logic Deign Using VHDL

What you'll learn

Basics of Digital Design
Combinational Logic design using VHDL
Sequential Logic Deign Using VHDL
Finite State Machines using VHDL
FPGA design Fundamentals

* Requirements

* Basics of Digital Design (AND
* OR
* NAND
* NOR gates
* flip flops
* counters and registers)
* Xilinx Webpack ISE software ( http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm )
* A PC with windows

Description

A course designed to teach the candidate the concepts of digital systems design using FPGAs. The design is taught using a Hardware Description Language (HDL) called as VHDL. The course will discuss in-depth all the components of VHDL and how different language constructs help us in designing hardware. The course will then give the student an option of doing real hardware experiments remotely or perform simulation experiments using the software that is available to download from the internet.

Who this course is for:

  • Electrical/ Electronics/ Electronics and Communication Engineering students [2nd, 3rd and Final Year]
  • Engineering Diploma Students [3rd and Final Year]
  • Working Professionals

Course content

6 sections • 34 lectures

Understanding VHDL 7 lectures

Introduction to FPGA Design Flow Preview 30:41

Xilinx Download Preview 05:49

Xilinx Installation Preview 07:04

VHDL Basics Preview 30:52

Lab 1a Switches LED Preview 13:24

Lab 1b Switches and LEDs simulation Preview 09:52

Test on Basics

Entity,Data modes,Architecture and Signals 8 lectures

Entity and Data Modes Preview 14:32

Architecture and Combinatiional Constructs Preview 15:29

Entity,Data Modes,Architecture and Signals

understanding Signals, when_else and with_select Statement Preview 26:28

Lab 2a When_else Statement Preview 10:15

Lab 2b When_else Simulation Preview 06:34

Lab 3a With_Select Statement Preview 13:56

Lab 3b With_Select Simulation Preview 06:06

Processes and Sequential Statements 7 lectures

Processes and Sequential Statements Preview 41:28

Making Sequential Circuits Preview 28:23

Lab 4a Processes and Sequential Statement Preview 14:50

Lab 4b Processes and Sequential Statements Simulation Preview 07:21

Lab 5a Processes and Case_Select Statement Preview 12:26

Lab 5b Processes and Case_Select Simulation Preview 04:34

Test on Process and Sequential Statements

Building Larger Designs Using Smaller Designs 4 lectures

Making Bigger designs from Smaller Designs Preview 18:54

Lab 6a Full Adder using Half Adder Preview 20:27

Lab 6b Full Adder using Half Adder Simulation Preview 05:04

Test on Making Bigger Designs from Smaller Designs

Clock dividers and Counters 4 lectures

Clock Dividers and Counters in VHDL Preview 21:37

Lab 7a Counters and Clock Dividers Preview 12:05

Lab 7b Counters and Clock Dividers Simulation Preview 05:05

Test on Clock Dividers and Counters

Designing Finite State Machines 4 lectures

Finite State Machines Preview 41:30

Lab 8a Voting Machine Design Preview 28:58

Lab 8b Voting Machine Simulation Preview 09:10

Test on FSM