Fpga Turbo Series Uart

Tags: FPGA

Develop a fully functional UART from start to finish and implement on your own FPGA development board

Last updated 2022-01-10 | 4.3

- Gain a solid understanding on how the UART protocol works.
- Implement a fully functional UART on their FPGA development board.
- Have a UART implementation in VHDL that they have created themselves.

What you'll learn

Gain a solid understanding on how the UART protocol works.

Implement a fully functional UART on their FPGA development board.

Have a UART implementation in VHDL that they have created themselves.

Improve their skill sets in FPGA development platforms

specifically Vivado's Design Suite.

Able to interpret

design

and implement a complex state machine.

* Requirements

* Download and install Xilinx Vivado Design Suite.
* Download and install TeraTerm or any other type of terminal emulator. There are instructions on how to install TeraTerm included in this course if you happen to get stuck.
* Basic understanding or exposure to VHDL.
* Basic understanding of digital circuits.
* Familiar with what a Field Programmable Gate Array (FPGA) is.

Description

This course will explain how the Universal Asynchronous Receiver Transmitter (UART) protocol can be used to transmit and receive information. The UART protocol structure is explained in great detail with many visual representations to help the students understand how a UART works. Once the UART protocol has been sufficiently explained to the students, they will then be guided through the FPGA design and development process in order to implement a fully functional UART on their FPGA development boards. This fully functional UART will be able to accept commands received over the UART serial port and act upon these commands. These actions will include being able to individually select which LED's are on and which ones are off, as well as being able to set the number displayed on the 7 segment display.

Students will be provided with VHDL design files that can be used as starting points for their UART design. Working with the provided design files and using the lectures as references the students will implement a fully functional UART on their development boards. The students will get to use Xilinx's development tools for the design and debugging of their UART implementations.

This course is geared towards students who have been exposed to VHDL, FPGA's, as well as a basic understanding of digital circuits. This is a great supplement to any engineering student who wants to improve upon their hardware design skills before entering the workforce. This course is also great for anyone who is currently employed in the field engineering. Also any electronic hobbyist would benefit greatly from this course!

Upon completing this course students will have all the necessary design files to implement a UART on virtually any FPGA with minimal modifications. Beings that the students will be designing and debugging their own code they will have very detailed knowledge of how this design works and will easily be able to adapt it so that they can add support for many more commands!

Who this course is for:

You should take this course if: You have completed my Learn VHDL and FPGA Development course
You should take this course if: You have prior experience working with VHDL and FPGA's
You should take this course if: You have been exposed to VHDL and FPGA's
You should not take this course if: You have no prior VHDL, FPGA, or digital circuit knowledge

Course content

8 sections • 23 lectures

Introduction to the Course 2 lectures

Introduction Preview 01:21

This lecture introduces the instructor as well as the material covered.

Board Compatibility Preview 01:24

This lecture talks about and discusses which FPGA development boards will work for this course, as well as which development boards are most ideal.

Universal Asynchronous Receiver Transmitter (UART) 5 lectures

Introduction to UART Preview 03:53

This lecture introduces the UART protocol and ways it is used.

UART Protocol Preview 04:42

This lecture discusses in detail the UART protocol and how a set of data is transmitted via UART.

ASCII Preview 03:13

This lecture talks about ASCII and how it is related to UART.

UART Transmission Example Preview 03:46

This lecture gives an example of how to transmit a message via UART.

UART Verification Preview 04:12

This lecture walks through the steps to verify that the UART on your development board is working correctly.

UART Transmitter FPGA Design 5 lectures

UART Transmitter Design Preview 07:42

This lecture discusses how the UART transmitter is designed and what the students will need to do in order to get the transmitter working.

UART Transmitter State Machine Design Preview 03:11

This lecture walks through and explains the UART transmitter's state machine design.

Creating UART Transmitter Vivado Project Preview 09:18

This lecture walks through step-by-step the process of creating a project in Xilinx's Vivado Design Suite, in order to develop a UART transmitter FPGA design.

UART Transmitter Design Guide Preview 04:09

This lecture explains in detail the theory and operation of the UART transmitter. By following the concepts discussed in this lecture students can complete the UART transmitter design.

UART Transmitter Simulation and Verification Preview 05:53

This lecture walks through the steps required to simulate your UART transmitter in Vivado in order to verify your design is working correctly.

UART Receiver FPGA Design 3 lectures

UART Receiver State Machine Design Preview 02:51

This lecture describes and explains the UART receiver state machine design in great detail.

Creating UART Receiver Vivado Project Preview 04:37

This lecture walks through step-by-step to create a project in Xilinx's Vivado Design Suite in order to implement the UART receiver FPGA design.

UART Receiver Simulation and Verification Preview 05:02

This lecture walks through the steps required to simulate your UART receiver in order to verify your design is working correctly.

UART Controller FPGA Design 3 lectures

UART Controller State Machine Design Preview 09:44

This lecture shows the UART controller state machine and explains what causes the transitions between states.

Creating UART Controller Vivado Project Preview 04:28

This lecture walks students through step-by-step showing them how to create a project in Xilinx's Vivado Design Suite, so they can implement the UART controller on their development board.

UART Controller Simulation and Verification Preview 05:46

This lecture walks through the steps required to simulate your UART receiver in order to verify your design is working correctly.

UART Demonstration 3 lectures

Programming the BASYS 3 Board Preview 03:42

This lecture walks students through the steps to program their development board. In this lecture the BASYS 3 board is being programmed.

UART Setup on the BASYS 3 Board Preview 03:30

This lecture shows the setup I used while programming and debugging the UART controller design.

UART Demonstration on the Basys 3 Preview 05:05

This lecture shows a demonstration of the fully functional UART running on a BASYS 3 development board.

Development Tools 1 lectures

Download and install Xilinx Vivado Tool Suite Preview 07:44

This lecture discusses the steps required to download and install Xilinx's Vivado design suite, the tool used to develop, simulate, and program the FPGA development board.